HW-V4SX35-VIDEO-SK-UK【PDF 46/112 页】VIRTEX-4 VIDEO STARTER KIT

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Chapter 4: Hardware Co-Simulation

first input port on the co-simulation block. An Outport with an index of 2 will be the

second output port on the co-simulation block.

R

?

Because Gateway blocks lack an explicit index or ordering in Simulink, these ports are

added to a run-time co-simulation block in alphabetical order. If a design contains

both Gateways and Inport/Outport blocks, the Gateway ports appear last (i.e., they

have a higher index).

Shared Register

A To Register, From Register or shared register pair can be generated and co-simulated in

FPGA hardware. Here a shared register pair is defined as a To Register block and From

Register block that specify the same name (e.g., Bar). See Figure 4-2 . In hardware, a shared

register is implemented using a synthesizable register component (for VHDL) or a module

(for Verilog).

Figure 4-2: Shared Register Pair

When a design that includes a shared register pair is compiled for hardware co-simulation,

the pair is replaced by a single register instance. Both sides of the register are attached to

user design logic ; that is, logic that originated from the original System Generator model. In

this case, control of the register is not shared between the PC and FPGA hardware since all

register ports are attached to user design logic. Compiling a shared register pair to

hardware is equivalent to compiling a System Generator Register or Delay block.

Compiling a single To Register or From Register block for hardware co-simulation results

in a different type of implementation. A single register is still created to replace the To or

From Register block. Only in this case, the register connects to both the PC and FPGA

memory map logic. The side of the register in the original model remains connected to user

design logic. The other side of the register attaches to memory map interface logic.

For designs that use hardware co-simulation, shared register pairs are typically distributed

between software and FPGA hardware. In other words, one half of the pair is implemented

in the FPGA, while the other half is simulated in software using a To or From Register

block. When data is written to a software To Register block, the hardware register is

updated to with the same data. Similarly, when data is written into the hardware register,

the same data is read by the From Register software block. A software shared register can

connect to a hardware shared register simply by specifying the name of the shared register

as it was compiled for hardware co-simulation.

Shared Memory

Compiling a shared memory block for hardware co-simulation adds an addressable block

of memory into the co-simulation memory map ( Figure 4-3 ). Shared memory blocks can be

configured with a lockable or unprotected access protection mode. This section touches on

both protection modes since they are involved during co-simulation semantics.

46

Video Starter Kit

UG217 (v1.5) October 26, 2006

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